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CY28326
FTG for VIA PT880 Serial Chipset
Features
* * * * * * Supports P4 CPUs 3.3V power supply Ten copies of PCI clocks One 48 MHz USB clock Two copies of 25 MHz for SRC/LAN clocks One 48 MHz/24 MHz programmable SIO clock * Three differential CPU clock pairs * SMBus support with Byte Write/Block Read/Write capabilities * Spread Spectrum EMI reduction * Dial-A-Frequency(R) features * Auto Ratio features * 48-pin SSOP package
Block Diagram
XIN XOUT PLL1 CPU_STP# IREF Power on Latch
/2
Pin Configuration[1]
REF[0:2]
CPUT[0:2] CPUC[0:2] 25MHz[0:1] AGP[0:2]
FS[A:D] VTTPWRGD# PCI_STP#
**FSA/REF0 **FSB/REF1 VDDREF XIN XOUT VSSREF *FSC/PCIF0 *FSD/PCIF1 *Mode/PCIF2 VDDPCI VSSPCI PCI0 PCI1 PCI2 PCI3 PCI4 VDDPCI VSSPCI *(PCI_STP#)/Ratio0/PCI5 *(CPU_STP#)/Ratio1/PCI6 48MHz **24_48_SEL/24_48MHz VSS48 VDD48
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDA VSSA IREF CPUT2 CPUC2 VSSCPU CPUT1 CPUC1 VDDCPU CPUT0 CPUC0 VSSSRC 25MHz1 25MHz0 VDDSRC *VTT_PWRGD/*PD# SD ATA SCLK SRESET# AGP2 VSSAGP VDDAGP AGP1/*RatioSel AGP0
CY2 8 3 2 6
PCI[0:6] PCI_F[0:2]
PLL2 MODE PD# SDATA SCLK WD Logic I2C Logic
48MHz 24_48MHz SRESET
48 Pin SSOP
Note: 1. Pins marked with [*] have internal 150k pull-up resistors. Pins marked with [**] have internal 150k pull-down resistors.
Cypress Semiconductor Corporation Document #: 38-07616 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised June 22, 2004
CY28326
Pin Definition
Pin No. 1 Name **FSA/REF0 PWR VDDREF Type I/O Description Power-on Bi-directional Input/Output. At power-up, FSA is the input. when VTT_PWRGD transitions to a logic high, FSA state is latched and this pin becomes REF0, buffered output copy of the device's XIN clock. Default Internal pull down. Power-on Bi-directional Input/Output. At power-up, FSB is the input. when VTT_PWRGD transitions to a logic high, FSB state is latched and this pin becomes REF1, buffered output copy of the device's XIN clock. Default Internal pull down. 3.3V Power supply for REF clock output. Oscillator Buffer Input. Connect to a crystal or to an external clock. Oscillator Buffer Input. Connect to a crystal. Do not connect when an external clock is applied at XIN. Ground for REF clock outputs Power-on Bi-directional Input/ Output. At power up, FSC is the input. When the VTT_PWRGD transitions to a logic high, FSC state is latched and this pin becomes PCIF0. Default Internal pull up. Power-on Bi-directional Input/ Output. At power up, FSD is the input. When the VTT_PWRGD transitions to a logic high, FSD state is latched and this pin becomes PCIF. Default Internal pull up. Power-on Bi-directional Input/ Output. At power up, MODE/PCIF2 is the input. When the power up, MODE state is latched and then pin9 becomes PCIF2, PCI clock output for PCI Device.Default pull-up, See Table 2 3.3V power supply for PCI clock output. Ground for PCI clock output. PCI clock outputs. Ratio0 Output/PCI5 Output. At power up when RatioSel (pin 26) strapping = "High" & MODE (pin 9) strapping="High", (PCI_STP#) Ratio0/PCI5 becomes PCI5 clock output. At power up when RatioSel (pin 26) strapping = "low" & MODE (pin 9) strapping ="High", (PCI_STP#)Ratio0/PCI5 becomes Ratio0 output to support North bridge over freq strapping function. Once MODE(pin 9) strapping="Low", then (PCI_STP#)Ratio0/PCI5 becomes PCI_STP#, Default = "PCI5" see Table 2, Default Internal pull up. Ratio1 Output/PCI6 Output. At power up when RatioSel(pin 26) strapping = "High" & MODE(pin 9) strapping="High", (CPU_STP#) Ratio1/PCI6 becomes PCI6 clock output. At power up when RatioSel (pin 26) strapping = "low" & MODE(pin 9) strapping ="High", (PCI_STP#)Ratio1/PCI6 becomes Ratio1 output to support North bridge over freq strapping function. Once MODE(pin 9) strapping="Low", then (PCI_STP#)Ratio1/PCI6 becomes CPU_STP#, Default = "PCI6" see Table 2, Default Internal pull up. 48 MHz Clock Output. Power-on Bi-directional Input/output. At power up 24_48_SEL is the input. When VTT_PWRGD is transited to logic high, 24_48_SEL state is latched and this pin becomes 24/48 MHz output, Default 24_48_SEL= "0", 48 MHz output.Default Internal pull down. Ground for 48 MHz clock output.
2
**FSB/REF1
VDDREF
I/O
3 4 5 6 7
VDDREF XIN XOUT VSSREF *FSC/PCIF0 VDDPCI VDDREF VDDREF
I I O PWR I/O
8
*FSD/PCIF1
VDDPCI
I/O
9
*MODE/ PCIF2
VDDPCI
I/O
10,17 11,18 12,13,14,15,16 19
VDDPCI VSSPCI PCI[0:4] *(PCI_STP#) VDDPCI Ratio0/PCI5
I I O O
20
*(CPU_STP#) VDDPCI Ratio1/PCI6
O
21 22
48 MHz
VDD48
O I/O
**24_48_SEL/ VDD48 24_48 MHz
23
VSS48
I
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CY28326
Pin Definition (continued)
Pin No. 24 25,29 26 Name VDD48 AGP0/AGP2 *RatioSEL /AGP1 VDDAGP VDDAGP PWR Type I O I/O AGP Clock Output. Power-on Bi-directional Input/output. At power up, RatioSel is the input. when the power supply voltage crosses the input threshold voltage, RatioSel state is latched and this pin becomes AGP clock output. Default pull-up. 3.3V power supply for AGP clock output. Ground for AGP clock output. System Reset Control Output. Serial clock input. Conforms to the Philips I2C specification. Serial clock input. Conforms to the Philips I2C specification of a Slave Receive/Transmit device. it is an input when receiving data. It is open drain output when acknowledging or transmitting data. VTT_PWRGD: 3.3V LVTTL input to determine when FS[D:A], MODE, RatioSEL and 24_48_SEL inputs are valid and ready to be sampled. PD#: Invokes powerdown mode. Default Internal pull up. Power for 25 MHz clock output. 3.3V Power Supply. 25 MHz Clock Output. Ground for 25 MHz clock output. CPU Clock outputs. Power for CPU clock output. Ground for CPU clock output. Current Reference. A precision resistor is attached to this pin, which is connected to the internal current reference. Ground for output. 3.3V Power Supply for output Description Power for 48MHz clock output.
27 28 30 31 32
VDDAGP VSSAGP SRESET# SCLK SDATA
I I O I I/O
33
*VTT_PWRG D/PD#
I
34 35,36 37 40 43 46 47 48
VDDSRC 25MHz[0:1] VSSSRC VDDCPU VSSCPU IREF VSSA VDDA VDDSRC
I O I O I I I I I
39,38,42,41,45,44 CPU[T/C][0:2] VDDCPU
Table 1. Frequency Table FS(D:A) FS(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PLL Gear Constant (Million) 25.00258122 37.50387182 75.00774365 37.50387182 75.00774365 75.00774365 75.00774365 75.00774365 18.75193591 25.00258122 37.50387182 37.50387182 18.75193591 25.00258122 37.50387182 37.50387182 Page 3 of 23
CPU (MHz) 110.0 146.6 220.0 183.3 233.3 266.6 333.3 300.0 100.9 133.9 200.9 166.9 100.0 133.3 200.0 166.6
AGP (MHz) 73.3 73.3 73.3 73.3 66.7 66.7 66.7 66.7 67.3 67.0 67.0 66.8 66.7 66.7 66.7 66.7
PCI (MHz) 36.6 36.6 36.6 36.6 33.3 33.3 33.3 33.3 33.6 33.5 33.5 33.4 33.3 33.3 33.3 33.3
SATA (MHz) 25.0 25.0 25.0 25.0 25.0 25.0 25.0 25.0 25.0 25.0 25.0 25.0 25.0 25.0 25.0 25.0
VCO (MHz) 660.00 586.68 440.00 733.33 466.67 533.33 666.67 600.00 807.2 803.4 803.6 667.6 800.00 800.00 800.00 666.67
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Table 2. Mode Ratio Setting Power-up Condition Mode 0 0 1 1 Table 3. Ratio mapping Table Power-up Frequency value CPU 100 133 200 166 AGP 66.6 66.6 66.6 66.6 FS1 0 0 1 1 FS[1:0] FS0 0 1 0 1 Ratio pin mapping Pin 20 0 0 1 1 Pin 19 0 1 0 1 RatioSel x x 0 1 Pin 19 PCI_STP# PCI_STP# Ratio0 PCI5 Pin I/O Setting Pin 20 CPU_STP# CPU_STP# Ratio1 PCI6
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. The interface can also be accessed during power down operation.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, Table 4. Command Code Definition Bit 7 0 = Block read or block write operation 1 = Byte read or byte write operation
block write and block read operation from any external I2C controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 4. The block write and block read protocol is outlined in Table 5 while Table 6 outlines the corresponding byte write and byte read protocol.The slave receiver address is 11010010 (D2h).
Description
(6:5) Device selection bits. Set = 00 (4:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 5. Block Read and Block Write protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 Bits Acknowledge from slave Byte Count - 8 bits (Skip this step if I2C_EN bit set) Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 Bits Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte Count from slave - 8 bits Page 4 of 23 Block Read Protocol Description
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Table 5. Block Read and Block Write protocol (continued) 46 .... .... .... .... Acknowledge from slave Data Byte /Slave Acknowledges Data Byte N -8 bits Acknowledge from slave Stop 38 46:39 47 55:48 56 .... .... .... ... Table 6. Byte Read and Byte Write protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 29 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeated start Slave address - 7 bits Read Acknowledge from slave Data from slave - 8 bits NOT Acknowledge Stop Byte Read Protocol Description Acknowledge Data byte 1 from slave - 8 bits Acknowledge Data byte 2 from slave - 8 bits Acknowledge Data bytes from slave / Acknowledge Data Byte N from slave - 8 bits NOT Acknowledge Stop
Byte Configuration Map
Byte 0: Control Register Bit 7 6 5 4 3 2 1 0 @Pup HW HW HW HW 0 1 1 1 Name/Pin Affected FSD FSC FSB FSA Test bit CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 Don't change, Default =0 CPU[T/C]2 Output Enable 0 = Disabled (tri-sate), 1 = Enabled CPU[T/C]1 Output Enable 0 = Disabled (tri-sate), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disabled (tri-sate), 1 = Enabled Description HW Frequency selection bits [3:0]. See table 2. Power up latched value
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Byte 1: Control Register Bit 7 6 5 4 3 @Pup 1 1 0 0 0 Name/Pin Affected FS3 FS2 FS1 FS0 FS_Override/FS(D:A) FS_Override 0 = Select operating frequency by FS(D:A) (HW Strapping) input bits, 1 = Select operating frequency by FSEL[3:0](SW Strapping) settings. CPU[T/C]2 Powerdown/CPUSTP# drive mode 0 = Driven in powerdown, 1 = Tri-state CPU[T/C]1 Powerdown/CPUSTP# drive mode 0 = Driven in powerdown, 1 = Tri-state CPU[T/C]0 Powerdown/CPUSTP# drive mode 0 = Driven in powerdown, 1 = Tri-state Description SW frequency selection bits [3:0]. See table 2.
2 1 0
0 0 0
CPU[T/C]2 CPU[T/C]1 CPU[T/C]0
Byte 2: Control Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name/Pin Affected PCIF[2:0] PCI[6:0] AGP[2:0] Test bit 48 MHz, 24/48 MHz Reserved REF[1:0] Test bit Description PCIF Clock Output Drive Strength 0 = Low drive strength, 1 = High drive strength PCI Clock Output Drive Strength 0 = Low drive strength, 1 = High drive strength AGP Clock Output Drive Strength 0 = Low drive strength, 1 = High drive strength Don't change, Default =0 48 MHz Clock Output Drive Strength 0 = Low drive strength, 1 = High drive strength Reserved REF Clock Output Drive Strength 0 = Low drive strength, 1 = High drive strength Don't change, Default =0
Byte 3: Control Register Bit 7 6 5 @Pup 0 1 1 Name/Pin Affected Spread Spectrum Sel CPU AGP PCIF PCI Spread Spectrum Selection
`000' = -1.25 ~ 0.25% `001' = -1.0% `010' = -0.75% `011' = -0.5% (default) `100' = 0.75% `101' = 0.5% `110' = 0.35% `111' = 0.25%
Description
4 3 2
0 0 0
AGP_SKEW1 AGP_SKEW0 CPU,AGP,PCIF,PCI
AGP Skew control, relative to PCICLK
01 = -300ps 10 = +300ps 11 = +450ps
Spread Spectrum Enable/Disable Function 0 = Spread spectrum disable 1 = Spread spectrum enable REF1 Output Enable 0 = Disabled, 1 = Enabled REF0 Output Enable 0 = Disabled, 1 = Enabled Page 6 of 23
1 0
1 1
REF1 REF0
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CY28326
Byte 4: Control Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name/Pin Affected 48 MHz 24_48 MHz PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 48 MHz Output Enable 0 = Disabled, 1 = Enabled 24_48 MHz Output Enable 0 = Disabled, 1 = Enabled PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled PCI1 Output Enable 0 = Disabled, 1 = Enabled PCI0 Output Enable 0 = Disabled, 1 = Enabled Description
Byte 5: Control Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name/Pin Affected AGP2 AGP1 AGP10 25 MHz1 25 MHz0 PCIF2 PCIF1 PCIF0 AGP2 Output Enable 0 = Disabled, 1 = Enabled AGP1 Output Enable 0 = Disabled, 1 = Enabled AGP0 Output Enable 0 = Disabled, 1 = Enabled 25 MHz1 Output Enable 0 = Disabled, 1 = Enabled 25 MHz0 Output Enable 0 = Disabled, 1 = Enabled PCIF2 Output Enable 0 = Disabled, 1 = Enabled PCIF1 Output Enable 0 = Disabled, 1 = Enabled PCIF0 Output Enable 0 = Disabled, 1 = Enabled Description
Byte 6: Control Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Name/Pin Affected Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description
Byte 7: Fract Aligner Control Register Bit 7 @Pup 1 Name/Pin Affected PCI6 PCI6 Output Enable 0 = Disabled, 1 = Enabled Description
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Byte 7: Fract Aligner Control Register (continued) Bit 6 5 4 3 2 1 0 @Pup 0 0 0 1 0 0 0 Name/Pin Affected Test bit Test bit Reserved Reserved Reserved Fract_Align1 Fract_Align0 Don't change, Default =0 Don't change, Default =0 Reserved Reserved Reserved AGP and PCI fixed frequency selection bit 1 AGP and PCI fixed frequency. This option does not incorporate spread spectrum. It is enabled through Fixed_AGP_SEL bits (B8b7)
Fract_align1 0 0 1 1 Fract_align1 0 1 0 1 AGP 66.6 75.0 75.0 85.7 PCI 33.3 37.5 37.5 42.8
Description
Byte 8: Control Register Bit 7 @Pup 0 Name/Pin Affected AGP Description AGP output frequency select mode. Selects the frequency source for AGP outputs. 0 = Set according to Frequency Selection Table 1 = Set according to Fractional Aligner Settings Program Fract Aligner values before setting this bit. Reserved This bit allows selection of the frequency setting that the clock will be restored to once the system is rebooted. 0 = Use hardware settings, 1 = use last SW table programmed values. This bit is set to "1" when the watchdog times out. It is reset to "0" when the system clears the WD_TIMER time stamp. Watchdog timer time stamp selection: 0000: Off 0001: 10msec 0010: 4 second
. . .
6 5
1 0
Reserved Recovery_Frequency
4 3 2 1 0
0 0 0 0 0
WD_Alarm WD_TIMER3 WD_TIMER2 WD_TIMER1 WD_TIMER0
1110: 28 seconds 1111: 30 seconds Byte 9: Control Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name/Pin Affected CPU_FSEL_N7 CPU_FSEL_N6 CPU_FSEL_N5 CPU_FSEL_N4 CPU_FSEL_N3 CPU_FSEL_N2 CPU_FSEL_N1 CPU_FSEL_N0 Description If Dial-A-Frequency Enable bit is set, the values programmed in CPU_FSEL_N[8:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. This setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the latched FS[D:A] register will be used. When it is set, the frequency ratio stated in the SEL[3:0] register will be used.
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Byte 10: Control Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name/Pin Affected CPU_FSEL_N8 CPU_FSEL_M6 CPU_FSEL_M5 CPU_FSEL_M4 CPU_FSEL_M3 CPU_FSEL_M2 CPU_FSEL_M1 CPU_FSEL_M0 Description Dial-A-Frequency Enable bit is set, the values programmed in CPU_FSEL_N[8:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. This setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the latched FS[D:A] register will be used. When it is set, the frequency ratio stated in the SEL[3:0] register will be used.
Byte 11: Control Register Bit 7 6 5 4 3 2 1 @Pup 0 0 1 0 0 0 HW Name/Pin Affected Dial_A_Frequency Enable Description Dial-A-Frequency output frequencies enabled 0 = Disabled, 1 = Enabled
WD Timer Reload & Reset To enable this function the register bit must first be set to "0" before toggling to "1" 0 = Do not reload, 1 =Reset timer but continue to count. Test bit Test bit Test bit Test bit 24-48 M_SEL Don't change, Default =1 Don't change, Default =0 Don't change, Default =0 Don't change, Default =0 "0" = 48 MHz, "1" = 24 MHz, default = "0", level can be change during BIOS boot up only. System will hang if this configuration is changed after system boots. Don't change, Default =1
0
1
Test bit
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CY28326
Crystal Recommendations
The CY28326 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the Table 7. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 50 ppm Stability (max.) 50 ppm Aging (max.) 5 ppm CY28326 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL).The following diagram shows a typical crystal configuration using the two trim capacitors. An
important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true.
Figure 1. Crystal Capacitive Clarification
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal.
Clock Chip (CY28326) Ci1
This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides.
Ci2 Pin 3 to 6p
Cs1
X1
X2
Cs2 Trace 2.8pF
XTAL Ce1 Ce2
Trim 33pF
Figure 2. Crystal Loading Example As mentioned previously, the capacitance on each side of the While the capacitance on each side of the crystal is in series crystal is in series with the crystal. This mean the total capacwith the crystal, trim capacitors(Ce1,Ce2) should be calcuitance on each side of the crystal must be 2 times the specified lated to provide equal capacitative loading on both sides. load capacitance (CL). Document #: 38-07616 Rev. *A Page 10 of 23
CY28326
Use the following formulas to calculate the trim capacitor values fro Ce1 and Ce2.
Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) CLe
Total Capacitance (as seen by the crystal)
=
1 ( Ce1 + Cs1 + Ci1 +
1
1 Ce2 + Cs2 + Ci2
)
CL .................................................. Crystal load capacitance CLe ................................................ Actual loading seen by crystal using standard value trim capacitors Ce .................................................. External trim capacitors Cs........................................... CStray capacitance (trace,etc) Ci ............. Internal capacitance (lead frame, bond wires etc)
powered down. All clocks are shut down in a synchronous manner so as not to cause glitches while transitioning to the low `stopped' state.
PD# - Assertion When PD# is sampled low by two consecutive rising edges of CPUC clock then all clock outputs (except CPU) clocks must be held low on their next high to low transition. CPU clocks must be driven high with a value of 2x Iref and CPUC undriven. Due to the state of internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete
PD# (Power-down) Clarification The PD# (Power Down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function. When PD# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also
PD# CPUT, 133MHz CPUC, 133MHz AGP, 66MHz 48MHz PCI, 33MHz SRC, 25MHz REF, 14.31818
Figure 3. Power-down Assertion Timing Waveforms
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PD# De-assertion The power-up latency between PD# rising to a valid logic `1' level and the starting of all clocks is less than 3.0 ms.
Tstable <1.8ms
PD# CPUT, 133MHz CPUC, 133MHz AGP, 66MHz 48MHz PCI, 33MHz SRC, 25MHz REF, 14.31818
Tdrive_PD# <300S, >200mV
Figure 4. Power-down De-assertion Timing Waveforms CPU_STP# Assertion The CPU_STP# signal is an active low input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by three
CPU_STP#
rising edges of the internal CPUT clock. The final states of the stopped CPU signals are CPUT = HIGH and CPUC = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to (Mult 0 `select') x (Iref), and the CPUC signal will not be driven. Due to the external pull-down circuitry, CPUC will be LOW during this stopped state.
CPUT CPUC
Figure 5. CPU_STP# Assertion Waveform CPU_STP# De-assertion The de-assertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than three CPU clock cycles.
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CPU_STP# CPUT CPUC
CPU Internal
Tdrive_CPU_STP#,10nS>200mV
Figure 6. CPU_STP# De-assertion Waveform PCI_STP# Assertion
[2]
The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function.
The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 7.)
PCI_STP# PCI_F
Tsu
PCI
Figure 7. PCI_STP# Assertion Waveform
PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI clocks to
Tsu
resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level.
PCI_STP# PCI_F
PCI
Figure 8. PCI_STP# Deassertion Waveform
Note: 2. The PCI STOP function is controlled by PCI_STP# pin number 19.
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F S[D:A] VT T _PW RG D PW RG D_VRM Device is not affected, VT T _PW RG D is ignored. And this pin become PD# function State 3 On On
VDD Clock G en Clock State State 0
0.2-0.3mS Delay State 1
W ait for VT T _PW RG D
Sample Sels State 2
Clock O utputs
O ff O ff
Clock VCO
Figure 9. VTT_PWRGD Timing Diagram
S1
S2 VTT_PWRGD = High
Delay >0.25mS
VDD_A = 2.0V
Sample Inputs straps
Wait for <1.8ms S0 S3 VDD_A = off
Power Off
Normal Operation
VTT_PWRGD = toggle
Enable Outputs
Figure 10. Clock Generator Power-up/Run State Diagram
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WATCHDOG TIMER PROGRAMMING
RESET WATCHDOG TIMER Set WD Timer Bits = 0 Clear W Alarm bit = 0 D
INITIALIZE WATCHDOG TIMER Set Frequency Revert Bit Set W Timer Bits D
CHANGE FREQBY SET SOFTWARE FSEL Set SW Freq_Sel bits Set FS override bit
CHANGE FREQ BY SET DIAL-AFREQUENCY Load M and N Registers Set Pro_Freq_EN = 1
WD timer Reload bit setting from 0 to 1
Set WD Timer Bits to Extend Time
YES
WD Alarm bit = 1
NO
System need Extend Time for next count
YES NO CLEAR WD TIMER Set W timer Bits = 0 D
Frequency Revert Bit = 0 Set Frequency to FS_HW_Latched
Frequency Revert Bit = 1 Set Frequency to FS_SW Setting
Exit WD Timer SRESET# = 0 for 3 msec
Reset & Revert Frequency back
Figure 11. Watch Dog timer flowchart for BIOS programming
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Situation 1 : Power on & Ratio initial by HW strapping
VCC3
MODE 20us POR(Power On Reset) 280us VTT_PWRGD When Power up Ratio Select PIN = "Lo" then PIN19,PIN20 become Ratio Function PIN Power up PIN20 default = Ratio 1 follow HW FSB Strapping Power up PIN19 default = Ratio 0 follow HW FSA Strapping Hi 1ms System Power OK PCI RESET
Ratio Select PIN
Lo
(PIN20)Ratio1/ PCI6 (PIN19)Ratio0/ PCI5
Lo
Figure 12. Situation 1: Power on & Ratio initial by HW strapping
P o w e r s e q u e n c e f o r R a t io P IN
S it u a t io n 2 : B IO S p r o g r a m m in g S W F S E L t a b le a n d S y s t e m r e s e t b y W a t c h d o g t im e r r e s e t f u n c t io n ( N O F r e q u e c n y r e c o v e r y ) .
VCC3 M ODE P O R (P o w e r O n R e s e t) Hi Hi
Hi
VTT_PW RG D
Hi Lo
R a t i o S e le c t P IN A f t e r B IO S p r o g r a m m i n g S W F S E L R a t io 1 s w it c h t o n e w S W F S 1 v a lu e ( P IN 2 0 ) R a t io 1 / P C I6 ( P IN 1 9 ) R a t io 0 / P C I5 S ys te m P o w e r OK PCI RESET S y s t e m S t r a p p in g F r e q R a t i o in t h is p o in t Hi A f t e r B IO S p r o g r a m m in g S W F S E L R a t io 0 s w i t c h t o n e w S W F S 0 v a lu e Hi 1ms
Figure 13. BIOS programming SW FSEL table and System reset by Watch timer reset function (NO Frequency recovery).
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CY28326
Situation 3 : Power on & Ratio PIN switch to PCI clock
VCC3
MODE 20us POR(Power On Reset) 280us VTT_PWRGD
Ratio Select PIN
1
When Power up Ratio Select PIN ="Hi" then PIN19,PIN20 become PCI clock PIN
(PIN20)Ratio1/ PCI6 (PIN19)Ratio0/ PCI5 1ms SystemPower OK PCI RESET
Figure 14. Power on & Ratio PIN switch to PCI clock
Absolute Maximum Conditions
Parameter VDD VDDA VIN TS TA TJ ESDHBM OJC OJA UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Relative to V SS Non Functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - 2000 36.92 83.52 V-0 1 Max. 4.6 4.6 VDD + 0.5 +150 70 150 - Unit V V VDC C C C V C/W C/W
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter VDD, VDDA VILI2C VIHI2C VIL Description 3.3 Operating Voltage Input Low Voltage Input High Voltage Input Low Voltage 3.3V 5% SDATA, SCLK SDATA, SCLK Condition Min. 3.135 - 2.2 VSS-0.5 Max. 3.465 1.0 - 0.8 Unit V V V V Page 17 of 23
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DC Electrical Specifications
Parameter VIH IIL VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD Description Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage High-Impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current At 200 MHz and all outputs loaded per Table 8 and Figure 15 except Pull-ups or Pull downs 0 < VIN < VDD IOL = 1 mA IOH = -1 mA Condition Min. 2.0 -5 - 2.4 -10 2 3 - 0.7VDD 0 - Max. VDD+0. 5 5 0.4 - 10 5 6 7 VDD 0.3VDD 350 Unit V A V V A pF pF nH V V mA
AC Electrical Specifications
Parameter Crystal TDC Description XIN Duty Cycle Condition The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When Xin is driven from an external clock source Measured between 0.3VDD and 0.7VDD As an average over 1s duration Over 150 ms Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from Vol = 0.175 to Voh = 0.525V 38 9.9970 7.4978 5.9982 4.9985 - - 175 - - Math averages Figure 15 Math averages Figure 15 660 -150 200 - -0.3 See Figure 15. Measure SE - Min. Max. Unit
47.5
52.5
%
TPERIOD TR / TF TCCJ LACC CPU at 0.7V TDC TPERIOD TPERIOD TPERIOD TPERIOD TSKEW TCCJ TR / TF TR TF VHIGH VLOW VOX VOVS VUDS VRB AGP
XIN period XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long Term Accuracy CPUT and CPUC Duty Cycle 100 MHz CPUT and CPUC Period 133 MHz CPUT and CPUC Period 166 MHz CPUT and CPUC Period 200 MHz CPUT and CPUC Period Any CPUT/C to CPUT/C Clock Skew CPUT/C Cycle to Cycle Jitter CPUT and CPUC Rise and Fall Times Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage
69.841 - -
71.0 10.0 500 300 62 10.003 7.5023 6.0018 5.0015 110 250 1300 550 550 850 - 550 VHIGH + 0.3 - 0.2
ns ns ps ppm % ns ns ns ns ps ps ps ps ps mv mv mv V V V
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AC Electrical Specifications (continued)
Parameter TDC TPERIOD TPERIOD THIGH TLOW TR / TF TSKEW TCCJ PCI/PCIF TDC TPERIOD TPERIOD THIGH TLOW TR / TF TSKEW TCCJ 48M TDC TPERIOD THIGH TLOW TR / TF TCCJ TSKEW 25M TDC TPERIOD THIGH TLOW TR / TF TCCJ TSKEW LACC REF TDC TPERIOD TR / TF TCCJ TSKEW Description AGP Duty Cycle Spread Disabled AGP Period Spread Enabled AGP Period AGP High Time AGP Low Time AGP Rise and Fall Times Any AGP to Any AGP Clock Skew AGP Cycle to Cycle Jitter PCI Duty Cycle Spread Disabled PCIF/PCI Period Spread Enabled PCIF/PCI Period PCIF and PCI High Time PCIF and PCI Low Time PCIF and PCI Rise and Fall Times Any PCI clock to Any PCI Clock Skew PCIF and PCI Cycle to Cycle Jitter Duty Cycle Period 48 MHz High Time 48 MHz Low Time Rise and Fall Times Cycle to Cycle Jitter Any 48 MHz to 48 MHz clock skew Duty Cycle Period 25 MHz High Time 25 MHz Low Time Rise and Fall Times Cycle to Cycle Jitter Any 25 MHz to 25 MHz Clock Skew 25MHz Long Term Accuracy REF Duty Cycle REF Period REF Rise and Fall Times REF Cycle to Cycle Jitter Any REF to REF clock skew Condition Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement @1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement @1.5V Measurement @1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement @1.5V Min. 44 14.9955 14.9955 4.5000 4.5000 0.5 - - 45 29.9910 29.9910 11.0 11.0 0.5 - - 45 20.8271 8.000 8.000 0.5 - - 45 39.998 17.9999 17.9999 0.4 - - - 45 69.827 0.45 - - Max. 56 15.0045 15.0799 8.0 8.0 2.0 550 500 55 30.0009 30.1598 15.0 15.0 2.0 700 550 55 20.8396 10.386 10.386 1.6 800 100 55 40.002 20.000 20.000 2.0 350 100 50 55 69.855 1.8 1600 500 Unit % ns ns ns ns ns ps ps % ns ns ns ns ns ps ps % ns ns ns ns ps ps % ns ns ns ns ps ps ppm % ns ns ps ps
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AC Electrical Specifications (continued)
Parameter Description Condition Min. - 10.0 0 Measured at crossing point VOX Measurement at 1.5V -100 1 Max. 1.8 - - 100 3 Unit ms ns ns ps ns ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up TSS TSH Stopclock Set-up Time Stopclock Hold Time
Special Skew & Jitter Specification Requirement CPU to CPU pin CPU group skew to pin Skew AGP to PCI pin to AGP group to PCI group skew pin Skew AGP must leading PCI
Table 8. Maximum Lumped Capacitive Output Loads Clock PCI Clocks AGP Clocks 48M Clock 25M Clock REF Clock Max Load 30 30 30 30 30 Unit pF pF pF pF pF
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CY28326
Test and Measurement Set-up
For Differential CPU and SRC Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
CPUT
33 4 9 .9 33
TPCB
M e a s u re m e n t P o in t
2pF
CPUC IR E F
475
TPCB
4 9 .9
M e a s u re m e n t P o in t
2pF
Figure 15. 0.7V Load Configuration
tD C 3 .3 V 2 .4 V 1 .5 V 0 .4 V 0V Tr Tf
O u tp u t u n d e r T e s t P ro b e Loas C ap
Figure 16. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement) Table 9. CPU Clock Current Select Function Board Target Trace/Term Z 50 Ohms Reference R, IREF - VDD (3*RREF) RREF = 475 1%, IREF = 2.32mA Output Current IOH = 6*IREF VOH @ Z 0.7V @ 50
Ordering Information
Part Number CY28326OC CY28326OCT CY28326OXC CY28326OXCT 48-pin SSOP 48-pin SSOP - Tape and Reel
Lead Free (Planned)
Package Type
Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C
48-pin SSOP 48-pin SSOP - Tape and Reel
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Package Drawing and Dimensions
48-lead Shrunk Small Outline Package O48
51-85061-*C
Dial-A-Frequency is a registered trademark of Cypress Semiconductor Corporation. Dial-A-Ratio is a trademark of Cypress Semiconductor Corporation. Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress.
CY28326
Document History Page
Document Title: CY28326 FTG for VIA PT880 Serial Chipset Document #: 38-07616 Rev. *A REV. ** *A ECN NO. 224103 237729 Issue Date See ECN See ECN Orig. of Change RGL RGL New Data Sheet Updated the AC Electrical Specs based on the characterization result Description of Change
Document #: 38-07616 Rev. *A
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